Quasanova

Name of the project: QUASANOVA

  • Description: QUAntum Simulations and Assessment of NanOdeVice Architectures
  • Context : Programme Nanotechnologies et Nanosustèmes (P2N)
  • Funding : Agence Nationale de la Recherche (1 113 506 €)
  • Duration of the project : 38 months (2011 – 2014)

Presentation:

During more than four decades, the scaling of the transistors induced an improvement of their performances. However, it is unanimously recognized that new architectures will be necessary to reach gate length of the order of 10 nm as planned in the next generations of transistors. In this context, the development of new simulation tools capable of guiding the semiconductor industry towards the most suitable architecture constitutes one of the essential issues in the next few years.
The device modeling became then a very competitive domain at the international level. Recently, several theoretical approaches capturing the quantum effects were developed, among which that of the non-equilibrium Green’s Function. Even if these approaches still miss precision in the description of few effects, they have reached a degree of maturity allowing relevant confrontation with experimental data.
This project proposes then for the first time a comparison between the most sophisticated theoretical approaches (i.e. based on non-equilibrium Green’s function formalism) and experimental measurements performed on transistors at the state of the art of the CMOS technology. The final goal is to analyze by means of models experimentally validated, the limits of the nanowire transistor performances and to estimate their possible advantages over planar FD-SOI (fully depleted Silicon On Insulator) devices.
We will then investigate the challenges to face for these two architectures by help of a consortium that merges complementary expertises ranging from simulation/modeling to fabrication and characterization of devices. The collective effort of partners will be devoted to address the following issues: (i) influence of the Si/SiO2 interface, (ii) influence of the electron-phonon coupling, (iii) study of hole transport: p-type transistors, (iv) experimental data: characterization of FD-SOI and nanowire devices at the state of the art of the CMOS technology (gate length from 10 to 20 nm), (v) comparison of the FD-SOI and nanowire architectures based on the theoretical models.
We will progressively develop a three-dimensional “experimentally validated” quantum transport modeling tool. It will allow to improve the analysis of the current characteristics and will be of a great relevance to optimize the architectures of the next generations of transistors. QUASANOVA project offers a natural means for fusing the expertise of different groups which could lead to breakthroughs in the understanding of nano-transistors as well as providing novel tools for the simulation and the design of nano-transistors for the next generations circuit and system applications.

Partners:

Partner 1 – Coordinator et scientific responsible of the project

Marc Bescond, IM2NP Dispositif Ultime sur Silicium
IM2NP UMR CNRS 6242 • Bât. IRPHE • 49, rue Joliot-Curie • BP 146 • Technopôle de Château-Gombert – 13384 Marseille Cedex 13 • France
Tel : +33 (0)4 96 13 97 31 • Fax : +33 (0)4 96 13 97 09
Mail : marc.bescondr@IM2NP.fr
im2np
www.IM2NP.fr

Partner 2

Christophe Delerue, IEMN, Groupe de Physique Théorique
IEMN UMR CNRS 8520 • Département ISEN • 41 Boulevard Vauban • 59046 Lille Cedex • France
Tel : +33 (0)3 20 30 40 53 • Fax : +33 (0)3 20 30 40 51
Mail : Christophe.delerue@isen.fr
iemn
www.iemn.univ-lille1.fr

Partner 3

Yann-Michel Niquet
INAC CEA Grenoble • 17 rue des Martyrs • Grenoble Cedex 9 • France
Tel : +33 (0)4 38 78 43 22 • Fax : 04 38 78 51 97
Mail : yann-michel.niquet@cea.fr
INAC
inac.cea.fr

Partner 4

Marco Pala, IMEP-LAHC
IMEP-LAHC UMR CNRS 5130 • MINATEC-INPG • 3 Parvis Louis Néel • BP 257 • 38016 Grenoble • France
Tel : +33 (0)4 56 52 95 49 • Fax : +33 (0)4 56 52 95 01
Mail : pala@minatec.inpg.fr
imep-lahc
www.imep.enserg.fr

Partner 5

Clément Tavernier, STMicroelectronics
STMicroelectronics SA • 850 rue Jean Monnet • 38926 Crolles Cedex • France
Tel : +33 (0)4 76 92 23 42 • Fax : +33 (0)4 76 92 37 84
Mail : clement.tavernier@st.com
logo_ST
www.st.com

Partner 6

Sylvain Barraud, CEA LETI Grenoble
LETI CEA Grenoble • 17 rue des Martyrs • BP 166 • 38054 Grenoble Cedex 9 • France
Tel : +33 (0) 38 78 98 45 • Fax: +33 (0) 438 78 94 56
Mail : sylvain.barraud@cea.fr
cea-leti
www-leti.cea.fr

Main publications: